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| 1 of 16 101001 features step sizes of 0.25 ns, 0.5 ns, 1 ns, 2 ns, 5 ns on-chip reference delay configurable as delay line, pulse width modulator, or free-running oscillator can delay clocks by a full period or more guaranteed monotonicity parallel or serial programming single 5v supply 16-pin dip or soic package pin assignment pin description in - input p0/q - parallel input p0 (parallel mode) - serial data output (serial mode) p1/clk - parallel input p1 (parallel mode) - serial input clock (serial mode) p2/d - parallel input p2 (parallel mode) - serial data input (serial mode) p3 - p7 - remaining parallel inputs gnd - ground out/ out - output ref/pwm - reference or pwm output p /s - parallel / serial programming select ms - output mode select le - input latch enable v cc - supply voltage description the ds1023 is an 8-bit programmable delay line similar in function to the ds1020/ds1021. additional features have been added to extend the range of applications: the internal delay line architecture has been revised to allow clock signals to be delayed by up to a full period or more. combined with an on-chip reference delay (to offset the inherent or ?step zero? delay of the device) clock phase can now be va ried over the full 0-360 degree range. ds1023 8-bit programmable timing element www.maxim-ic.com in le q/p0 clk/p1 d/p2 p3 p4 gnd 16 15 14 13 12 11 10 9 v cc out/out ref/pwm p/s p7 p6 ms p5 1 2 3 4 5 6 7 8 ds1023 300-mil dip ds1023s 300-mil soic
ds1023 2 of 16 on-chip gating is provided to allow the device to provide a pulse width modul ated output, triggered by the input with duration se t by the programmed value. alternatively the output signal may be inverted on ch ip, allowing the device to perform as a free-running oscillator if the output is (exter nally) connected to the input. programming the device programming is identical to the ds1020/ds 1021. note, however, that the serial clock and data pins are shared with th ree of the parallel input pins. the p /s pin controls the same function as ?mode select? on the ds1020/ds 1021 (but with reversed polarity). a low logic level on this pin enables the parallel programming mode. le must be at a high logic level to alter the programmed value; when le is taken low the data is latched internally and the parallel data inputs may be altered without affecting the progra mmed value. this is useful for multiplexed bus applications. for hard-wired appli cations le should be tied to a high logic level. when p /s is high serial programming is enabled. le must be held high to enable loading or reading of the internal register, during which time the delay is determined by the previously programmed value. data is clocked in msb to lsb order on the rising ed ge of the clk input. data transfer ends and the new value is activated when le is taken low. parallel mode ( p /s = 0) in the parallel programming mode, the output of the ds1023 will reproduce the logic state of the input after a delay determined by the state of the ei ght program input pins p0 - p7. the parallel inputs can be programmed using dc levels or computer-generated data. for infrequent modification of the delay value, jumpers may be used to connect the input pins to v cc or ground. for applications requiring frequent timing adjustment, dip switches may be used. the latch enable pin (le) must be at a logic 1 in hardwired implementations. maximum flexibility is obtained when the eight parallel programming bits are set using computer- generated data. when the data setup (t dse ) and data hold (t dhe ) requirements are observed, the enable pin can be used to latch data supplied on an 8-bit bus. latch enable must be held at a logic 1 if it is not used to latch the data. after each change in delay value, a settling time (t edv or t pdv ) is required before input logic levels are accurately delayed. serial mode ( p /s = 1) in the serial programming mode, the output of th e ds1023 will reproduce the logic state of the input after a delay time determined by an 8-bit value clocked into serial port d. while observing data setup (t dsc ) and data hold (t dhc ) requirements, timing data is loaded in msb-to-lsb order by the rising edge of the serial clock (clk). the latch enable pin (le) must be at a logic 1 to load or read the internal 8-bit input register, during which time the delay is determined by the last va lue activated. data transfer ends and the new delay value is activated when latch enable (le) returns to a logic 0. after each change, a settling time (t edv ) is required before the delay is accurate. as timing values are shifted into the serial data input (d), the previous contents of the 8-bit input register are shifted out of the serial output pin (q) in msb-to-lsb order. by connecting the serial output of one ds1023 to the serial input of a second ds1023, multiple devices can be daisy-chained (cascaded) for programming purposes (figure 1). the total number of serial bits must be eight times the number of units daisy-chained and each group of 8 bits must be sent in msb-to-lsb order. ds1023 3 of 16 applications can read the setting of the ds1023 delay li ne by connecting the serial output pin (q) to the serial input (d) through a resistor with a value of 1 to 10 kohms (figure 2). since the read process is destructive, the resistor restores the value read and provides isolation when writing to the device. the resistor must connect the serial output (q) of the last device to the serial input (d) of the first device of a daisy chain (figure 1). for serial readout with automa tic restoration through a resistor, the device used to write serial data must go to a high impedance state. to initiate a serial read, latch enable (le) is taken to a logic 1 while serial clock (clk) is at a logic 0. after a waiting time (t eqv ), bit 7 (msb) appears on the serial output (q). on the first rising (0 --> 1) transition of the serial clock (clk), bit 7 (msb) is rewritten and bit 6 appears on the output after a time t cqv . to restore the input register to its original state, this clocking process must be repeated eight times. in the case of a daisy chain, the process must be repeated eight times per package. if the value read is restored before latch enable (le) is returned to logic 0, no settling time (t edv ) is required and the programmed delay remains unchanged. since the ds1023 is a cmos design, unus ed input pins (p3 - p7) must be connected to well-defined logic levels; they must not be allowed to float. serial output q/p0 s hould be allowed to float if unused. cascading multiple devices (daisy chain) figure 1 serial readout figure 2 reference delay in all delay lines there is an inherent, or ?step ze ro?, delay caused by the propagation delay through the input and output buffers. in this device the step zero delay can be quite large compared to the delay step size. to simplify system design a reference dela y has been included on chip which may be used to compensate for the step zero delay. in practice this means that if the device is supplied with a clock, for example, the minimum programmed output delay is effectively zero with respect to the reference delay. ds1023 4 of 16 for highest accuracy it is strongly recommended that the reference delay is used. variations in input voltage levels and transition times can significantly alter the measured delay from input to output. this effect is totally removed if the reference delay output is used. furthermore, adverse effects on step zero delay caused by process temperature coefficients are also cancelled out. input pulse duration the internal architecture of the ds1023 allows the out put delay time to be considerably longer than the input pulse width (see ac specifications). this feature is useful in many applications, in particular clock phase control where delays up to and bey ond one full clock period can be achieved. mode select the ds1023 has four possible output functions but onl y two output pins. the functionality of the two output pins is determined by the mode select (ms) pin. ms = 0 figure 3 output function name pin number reference output ref 9 delayed output out 15 out is a copy of the input waveform that is dela yed by an amount set by the programmed values (table 1). a programmed value of zero will still result in a non-zero delay as indicated in the step zero delay specification. the signal on out is the same polarity as the input. ref is a fixed reference delay. it also is a copy of the input waveform but the delay interval is fixed to a value approximately equal to the step zero value of the device (as shown in the reference delay specification). in fact the device is trimmed to ensure that the reference delay is always slightly longer than the step zero value (by 1.5 ns typically). ds1023 5 of 16 ms = 1 figure 4 output function name pin number pulse width modulated output pwm 9 delayed and inverted output out 15 pwm is an output triggered by the rising edge of the input waveform. after a time interval approximately equal to the step zero delay of the device the pwm output will go high. the output will return to a low level after a time interval determined by the programmed values (table 1). hence output pulse widths can be obtained from (nearly) zero to the full delay ra nge of the device. in practice the minimum output pulse width is limited by the response time of the device to approximately 5ns. pr ogrammed values less than this will result in degradation of the output high level voltage until ultimately no discernible output pulse is produced. the frequency/repetition rate of the output is determined by the input frequency. the input pulse width can be shorter than the output pulse width, and is limited only by the minimum input pulse width specification. the pwm function is not ?re-tr iggerable?, subsequent input trigger pulses should not be present until the output has returned to a low level. out is an inverted copy of the input waveform th at is delayed by an amount set by the programmed values (table 1). a programmed valu e of zero will still result in a non-zero delay as indicated in the step zero delay specification. the out pin may also be externally conn ected to the input pin to produce a free-running oscillator. the frequency of oscillation is determined by the programmed delay value of the device (see table 2). ds1023 6 of 16 functional block diagram figure 5 delay line detail (conceptual) - ds1023-200, ds1023-500 figure 6 ds1023 7 of 16 delay line detail (conceptual) - ds1023-25, ds1023-50, ds1023-100 figure 7 part number table table 1 delays ranges and tolerance (all times measured in ns) part number step size max. delay time (1)/ max. output pulse width (2) maximum deviation (3) maximum i/p freq minimum i/p pulse width ds1023-25 0.25 63.75 1 25 mhz 20 ds1023-50 0.50 127.5 2 25 mhz 20 ds1023-100 1.0 255 4 25 mhz 20 ds1023-200 2.0 510 8 25 mhz 20 ds1023-500 5.0 1275 20 10 mhz 50 1. in ?normal? mode (ms=0). measured with respect to ref output. the minimum delay time is zero (or less, by 1.5 ns typically) 2. in pwm mode (ms=1). the minimum output pulse wi dth for reliable operati on is 5 ns; programmed values less than this may produce reduced output voltage levels or no output at all. 3. this is the deviation from a straight line drawn between the step zero value and the maximum programmed delay time. oscillator configuration table 2 part number step size (4) minimum o/p frequency (5) maximum o/p frequency (5) ds1023-25 0.5 6.6 mhz 22 mhz ds1023-50 1.0 3.6 mhz 22 mhz ds1023-100 2.0 1.9 mhz 22 mhz ds1023-200 4.0 0.98 mhz 22 mhz ds1023-500 10.0 0.4 mhz 22 mhz 4. step size in output period (in ns). 5. maximum output frequency depends on the actual step zero delay value, worst case values are shown in the table. the output period is given by: 2 * t d where: t d = absolute delay value. ds1023 8 of 16 dallas semiconductor test circuit figure 8 test setup description figure 8 illustrates the hardware configuration used for measuring the timing parameters of the ds1023. the input waveform is produced by a precision pulse generator under soft ware control. time delays are measured by a time interval counter (20 ps resolu tion) connected to the out put. the ds1023 serial and parallel ports are controlled by interfaces to a central computer. all measurements are fully automated with each instrument controlled by the computer over an ieee 488 bus. test conditions input: ambient temperature: 25 c 3 c supply voltage (v cc ): 5.0v 0.1v input pulse: high = 3.0v 0.1v low = 0.0v 0.1v source impedance: 50 ohms max. rise and fall time: 3.0 ns max. (measured between 0.6v and 2.4v) pulse width: 500 ns period: 1 s note: above conditions are for test only and do not rest rict the operation of the device under other data sheet conditions. output: output is loaded with a 74f04. delay is measured be tween the 1.5v level of the rising edge of the input signal and the 1.5v level of the corresponding edge of the output. ds1023 9 of 16 absolute maximum ratings* voltage on any pin -1.0v to +7.0v operating temperature range 0 c to 70 c storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds short circuit output current 50 ma for 1 second * this is a stress rating only and f unctional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteri stics (0c to 70c; v cc = 5v 5%) parameter symbol min typ max units notes supply voltage v cc 4.75 5 5.25 v high level input voltage v ih 2v cc +0.5 v low level input voltage v il -0.5 0.8 v input leakage current (0 ds1023 11 of 16 ac electrical characteristics ? ds1023-50 delay specifications (t a = 0 c to 70 c; v cc = 5v 5%) parameter symbol min typ max units notes step zero delay -absolute -wrt ref t d0 t dref0 -2 16.5 -1.5 22 0 ns ns 1, 13 2, 14 reference delay t ref 18 22 ns 3, 13 delay step size t step 0 0.5 1.5 ns 4 maximum delay -absolute -wrt ref t dmax t dref 139 123 144 127.5 154 132 ns ns 5, 13 6, 14 delay matching, rising edge to falling edge -1 +1 ns 15 integral non-linearity (deviation from straight line) t err -2 0 +2 ns 7 out delta delay t inv0 012ns8 in high to pwm high t pwm0 16.5 22 ns 9, 13 minimum pwm output pulse width t pwm 5ns10 minimum input pulse width t wi 20 ns 11 minimum input period 40 ns 12 input rise and fall times t r , t f 01 s 16 ac electrical characteristics ? ds1023-100 delay specifications (t a = 0 c ? 70 c; v cc = 5v 5%) parameter symbol min typ max units notes step zero delay -absolute -wrt ref t d0 t dref0 -2 16.5 -1.5 22 0 ns ns 1, 13 2, 14 reference delay t ref 18 22 ns 3, 13 delay step size t step 0 1 1.5 ns 4 maximum delay -absolute -wrt ref t dmax t dref 262 247 272 255 285 263 ns ns 5, 13 6, 14 delay matching, rising edge to falling edge -1 +1 ns 15 integral non-linearity (deviation from straight line) t err -4 0 +4 ns 7 out delta delay t inv0 012ns8 in high to pwm high t pwm0 16.5 22 ns 9, 13 minimum pwm output pulse width t pwm 5ns10 minimum input pulse width t wi 20 ns 11 minimum input period 40 ns 12 input rise and fall times t r , t f 01 s 16 ds1023 12 of 16 ac electrical characteristics - ds1023-200 delay specifications (t a = 0 c - 70 c; v cc = 5v 5%) parameter symbol min typ max units notes step zero delay -absolute -wrt ref t d0 t dref0 -2 16.5 -1.5 22 0 ns ns 1, 13 2, 14 reference delay t ref 18 22 ns 3, 13 delay step size t step 1.5 2 2.5 ns maximum delay -absolute -wrt ref t dmax t dref 509 494 527 510 548 526 ns ns 5, 13 6, 14 delay matching, rising edge to falling edge -1 +1 ns 15 integral non- linearity (deviation from straight line) t err -8 0 +8 ns 7 out delta delay t inv0 012ns8 in high to pwm high t pwm0 16.5 22 ns 9, 13 minimum pwm output pulse width t pwm 5ns10 minimum input pulse width t wi 20 ns 11 minimum input period 40 ns 12 input rise and fall times t r , t f 01 s 16 ac electrical characteristics ? ds1023-500 delay specifications (t a = 0 c ? 70 c; v cc = 5v 5%) parameter symbol min typ max units notes step zero delay -absolute -wrt ref t d0 t dref0 -2 16.5 -1.5 22 0 ns ns 1, 13 2, 14 reference delay t ref 18 22 ns 3, 13 delay step size t step 456ns maximum delay -absolute -wrt ref t dmax t dref 1250 1235 1292 1275 1337 1315 ns ns 5, 13 6, 14 delay matching, rising edge to falling edge -1 +1 ns 15 integral non- linearity (deviation from straight line) t err -20 0 +20 ns 7 out delta delay t inv0 012ns8 in high to pwm high t pwm0 16.5 22 ns 9, 13 minimum pwm output pulse width t pwm 5ns10 minimum input pulse width t wi 50 ns 11 minimum input period 100 ns 12 input rise and fall times t r , t f 01 s 16 ds1023 13 of 16 notes: 1. delay from input to output with a programmed delay value of zero. 2. this is the relative delay between ref and out. the device is trimmed such that when programmed to zero delay the out output will always appear before the ref output. this parameter is numerically equal to t d0 -t ref . (see figure 15). 3. the reference delay is closely matched to the step zero delay to allow relative timings down to zero or less. 4. this is the worst case condition when the subdac switches from its maximum to minimum value. all other steps are 0.5 lsb. this comment does not apply to -200 and -500 devices which do not use a subdac. (see figure 14) 5. this is the actual measured delay from in to out. this parameter will exhibit greater temperature variation than the relative delay parameter. 6. this is the actual measured delay with respect to the ref output. this parameter more closely reflects the programmed delay value than the absolute delay parameter. (see figure 15). 7. this is the maximum deviation from a straight lin e response drawn between the step zero delay and the maximum programmed delay. therefore it is indicative of the maximum error in the measured delay versus the programmed delay with respect to the ref output. the absolute delay measurement from in to out will in addition have an offset error equal to the step zero delay and its tolerance. (see figure 13). 8. change in delay value when the inverted output is selected instead of the normal, non-inverting, output. 9. in pwm mode the delay between the rising edge of the input and the rising edge of the output. 10. the minimum value for which the pwm pulse widt h should be programmed. narrower pulse widths may be programmed but output levels may be impaired and ultimately no output pulse will be produced. 11. this is the minimum allowable interval between tr ansitions on the input to assure accurate device operation. this parameter may be violated but timing accuracy may be impaired and ultimately very narrow pulse widths will result in no output from the device. 12. this parameter applies to normal delay mode only. when a 50% duty cycle input clock is used this defines the highest usable clock frequency. when asymmetrical clock inputs are used the maximum usable clock frequency must be reduced to conf orm to the minimum input pulse width requirement. in pwm mode the minimum input period is equal to the step zero delay and the programmed delay (t do + t d ). 13. measured from rising edge of the input to the rising edge of the output (t dr ). 14. from rising edge to rising edge. 15. this is the difference in measured delay between rising edge (input to output), t dr and falling edges (input to output), t df . 16. faster rise and fall times will give the greatest accuracy in measured delay. slow edges (outside the specification maximum) may result in erratic operations. ds1023 14 of 16 terminology period: the time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t wi (pulse width): the elapsed time on the pulse betw een the 1.5v point on the leading edge and the 1.5v point on the trailing edge, or the 1.5v point on the tr ailing edge and the 1.5v point on the leading edge. t rise (input rise time): the elapsed time between the 20 % and the 80% point on the leading edge of the input pulse. t fall (input fall time): the elapsed time between the 80 % and the 20% point on the trailing edge of the input pulse. t d (time delay): the elapsed time between the 1.5v poi nt on the edge of an input pulse and the 1.5v point on the corresponding edge of the output pulse. timing diagram: non-latched parallel mode ( p /s = 0, le = 1) figure 10 timing diagram: latched parallel mode ( p /s = 0) figure 11 ds1023 15 of 16 timing diagram: serial mode ( p /s = 1) figure 12 delay vs programmed value figure 13 t do t dmax (measured) ds1023 16 of 16 detailed response characteristics figure 14 delay parameters figure 15 notes: 1. the device is trimmed such that t dref = 255 * (nominal step size). 2. since t do is trimmed to be less than t ref , the actual step size will be slightly above the nominal value. 3. consequently the range of absolute delay values (t dmax -t do ) will also exceed the nominal range by an amount equal to t dref0 . |
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